Referring to FIG. 1, a semiconductor integrated circuit generally has a structure consisting of a substrate on which a number of layers are fabricated. Lowermost are one or more semiconductor layers 12 in which a plurality of semiconductor devices and other electronic devices are fabricated. Next is a dielectric layer 14, followed by an interconnect layer or metallization layer 16. (Integrated circuits often include a number of alternating dielectric and metallization layers, but only one is shown here for sake of illustration.)
The interconnect layer 16 includes a plurality of interconnect lines or conductor lines 18 whose function is to electrically connect a first device on the semiconductor layer 12 to a second such device. A plug 20 extends vertically through the dielectric layer 14 to electrically connect the first device to the interconnect line 18. The interconnect lines 18 and plugs 20 are fabricated of a material having high electrical conductivity, typically metal or doped semiconductor material.
After the semiconductor devices are fabricated in the semiconductor layer 12, the remaining layers typically are fabricated by the following steps. First, a layer of dielectric 14 is deposited to cover the entire surface of the semiconductor layer 12. Second, a vertical hole called a "via" is etched in the dielectric at each location where a plug is to be created. Third (optional), an extremely thin barrier layer and/or wetting layer 21 is deposited in each via. Fourth, a metal or other conductive material is deposited to fill each via to form the plugs 20. Fifth, a blanket layer of metal or other conductive material is deposited over the substrate. The fourth and fifth steps may be performed as a single deposition step. Sixth, resist material is deposited and patterned over the blanket conductive layer so as to cover the areas of the conductive material which are to become the interconnect lines. Finally, the blanket conductive layer is etched to remove the conductive material from all surfaces not covered by resist, thereby creating the interconnect lines.
A problem with conventional processes for forming an interconnect line is that the process of etching the edge 22 of the interconnect line can undesirably etch part of the plug 20, creating a void 24 in the plug as shown in FIGS. 2A and 2B. Such voids can be created when the etching process is continued too long (see FIG. 2A), or when the interconnect line is misaligned relative to the plug so that one edge 22 of the interconnect line is too close to, or fails to overlap, the adjacent edge of the plug (see FIG. 2B).
The risk of creating voids caused by over-etching or misalignment is highest if the interconnect line is no wider than the plug, i.e., a "zero overlap" interconnect, as shown in FIG. 2A. However, "zero overlap" interconnect lines are desirable to maximize the density of components on an integrated circuit. Therefore, methods have been developed to prevent voids in plugs beneath "zero overlap" interconnects.
One conventional method of preventing the interconnect etch process from etching into the plug is to fabricate the plug and interconnect lines of different materials. The edge of the interconnect then can be chemically etched using an etchant which does not significantly etch the plug material. Specifically, plugs and interconnect lines conventionally are fabricated of tungsten and aluminum, respectively. Chlorine is much more reactive with aluminum than with tungsten. Therefore, the edges of the aluminum interconnects can be etched with chlorine without significantly etching the tungsten plugs.
However, the method described in the preceding paragraph is disadvantageous in at least two respects. One disadvantage is that it precludes using the best conductor material for both the plugs and the interconnects. Specifically, aluminum is the preferred material for both the plugs and the interconnect lines because aluminum has a higher conductivity (lower resistivity) than other materials conventionally used for fabricating plugs, such as tungsten. Another disadvantage is that the contact between two different plug and interconnect materials can be unreliable.
When both the plugs and the interconnect lines are fabricated of the same material, such as aluminum, a conventional method of preventing the interconnect etch process from creating a void in the plug is to compromise the goal of "zero overlap" interconnect lines. Specifically, the interconnect lines are fabricated with extra width (labelled as "X" in FIG. 1) overlapping the dielectric on all sides of the plug, so that a certain amount of excessive etch time or misalignment between the interconnects and the plugs can be tolerated without etching into the plug. Of course, a disadvantage of this method is that the overlap "X" wastes space on the integrated circuit, thereby reducing the number of semiconductor devices which can be fabricated on an integrated circuit having a given surface area.